Baya- SoC Intgration Platform, IP-XACT 1685, UPF 3, Lib, Verilog and VHDL Parsers, Translators & Converters, Datemodel and Writers
Baya - Auto Integration of SoC Components with IP-XACT & Tcl API
Flattens the specified verilog module by removing the hierarchies. It works both for RTL and netlist.
Generates verilog testbench for a given module along with random testvectors ...
Generates VHDL testbench for a given entity along with random testvectors ...
Parses Veriog RTL and populates its object model which comes with a rich set of APIs to access design information.
Parses Veriog Netlist and populates its object model which comes with a rich set of APIs to access design information.
Parses synthesizable subset of VHDL and populates its object model which comes with a rich set of APIs to access design information.
Reads Verilog and VHDL files and prints out the sorted file list by analyzing dependencies. Supports VHDL configurations and mixed HDL
Verilog Preprocessor to resolve macros like nested `ifdef , `define
Verilog Hierarchy Creation Tool to group a list of instances in RTL or enlist. This creates a new wrapper by encapsulating the instance
Verilog Hierarchy Removal Tool to ungroup all the instances in a given module
Removes continuous assignment statements in a given netlist
Utility to find instances or nets matching with the given regular expression as their names
Utility to race the clock and reset trees in a given netlist or structural design
VHDL to SystemC translator which first converts the VHDL into Verilog and then converts the internal Verilog into SystemC
Tool to generate Verilog wrapper by instantiating the specified module- flattens/splits multidimensional ports and SV interfaces while instantiating original module.
Tool to generate VHDL wrapper by instantiating the specified entity- flattens/splits multidimensional array and record type ports
Tool to compare the interfaces ( ports, parameters, SV interfaces ) between two versions of a Verilog module or two similar modules.
Tool to compare the interfaces ( ports, generics ) between two versions of a VHDL entity or two similar entities.
DesignProfiler - Tool to profile an IP or a subsystem. It stores IP/SS metadata like top module name, clock, reset, input/output delay, false path, multi cycle path, scan clock, scan enable, scan style, power management techniques, power number, area number, technology node ...
Flattens the given list of hierarchical instances- this removes hierarchy by pulling the contents in the higher level
Library to parse VCD file and populate datamodel and APIs to access the information and print it back
Tool to convert Verilog into SystemC keeping the original structure as much as possible.
Tool to convert VHDL into Verilog by keeping the same structure and function for ease of correlation
Tool to create IP-XACT Component or Design from a Verilog Module
Tool to create IP-XACT Component from a VHDL Entity
Tool to convert Verilog into VHDL by keeping the same structure and function for ease of correlation.
Verilog Document Generator from the RTL definition of an IP/SubSystem. Use DesignPlayer Hierarchy Brower to create hierarchy snapshot to review design.
Translators and
converters
Verilog/VHDL Utilities
Parsers and
Generators
Tool to create VHDL Entity from IP-XACT Component
Tool to convert IP-XACT into Verilog module
Creates IP-XACT Address Block file from the legacy XLS/CSV based Register Management system.
Validates IP-XACT Component's ports and parameters with the associated Verilog/VHDL Module/Entity's ports and parameters
Java based simple .lib parser, supports the widely used set of constructs.
All the above listed 3 groups of tools are available in one single bundle named DesignPlayer, click here to download this.
Converts IP-XACT Address Block file into XLSX for review and documentation purpose
Converts IP-XACT Bus Definition / BusInterface into SystemVerilog Interface
Verilog empty/blackbox module generator keeping the includes, ports and parameters intact.
Create Liberty .lib library from verilog module
Converts Liberty .lib Cells into empty verilog modules
Java based Unified Power Format, UPF parser and Editor with API
Uniquifies Verilog by prependin given prefix with modules, interfaces, classes, structures and their references
Merges specific instances from different modules to one module
