Baya- AI Enabled SoC Intgration Platform, IP-XACT 1685, UPF, Verilog and VHDL Parsers, Translators & Converters, Datamodel and Re-Writers
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Baya - Auto Integration of SoC Components with IP-XACT & Tcl API
If you have any question concerning bug fixes, new features and  enhancements, please don't hesitate to contact. You will get the best solutions at the earliest.
    This tool takes the Verilog RTL file(s) along with other options including defines if any and writes out the preprocessed verilog file(s). This has been developed in Java( 1.6.x ) in order to make it platform independent and bundled as an executable JAR file  which can be directly used from the 'lib' directory in the downloaded tar or ZIP file. Example-

 source setup_env.('csh' or 'sh' or 'bat' as applicable ) 

Alternatively, for Unix
setenv EDAUTILS_ROOT /usr/user1/DesignPlayer-linux.x86/01MAY2014 ( installation dir )
set path = ( $EDAUTILS_ROOT/bin $path )

and for Windows

set EDAUTILS_ROOT=D:\tmp\DesignPlayer-win32.x86_64\01MAY2014 ( installation dir )
set PATH="%path%;%EDAUTILS_ROOT%\bin"

 preprocessverilog -in foo.v [-out preprocessed_foo.v] [+incdir+dir1+dir2]
[+define+macro1+macro2]

                                     OR

java com.eu.miscedautils.verilogparser.PreProcessVerilog -in foo.v [-out preprocessed_foo.v] [+incdir+dir1+dir2] [+define+macro1+macro2]



           If you do not use the -out switch then the result will be dumped in a directory name VlogPP inside the run directory. 
           If you have multiple input files then list all of those in a startup file provide that startup file with -f switch instead of -in switch and do not specify the output file name. All the preprocessed files will be written inside the dir named 'VlogPP' in the run directory.
         Go through the examples to get a better understanding of this tool. The examples are pretty comprehensive and covers wide range of possible scenario. Send mails to help@edautils.com if you need any assistance.

    Go to the installation directory i.e the directory where this README file resides and run the runme.csh script.


Get details by executing it as 'preprocessverilog -help

Send your feedback/queries to  help@edautils.com .


The collection of tools and utilities fills a real void in EDA. The baya tool is exactly what we had been looking for to assemble large top-level modules in Verilog. The GUI and high-level TCL commands are intuitive, allowing designers to get started immediately and feel right at home. It was straightforward to quickly reproduce a module previously done with a Perl-to-Verilog utility that was hard to use and maintain. The support from Kanai is excellent. He responds quickly and is a pleasure to deal with. Nice work, Kanai!”-Michael Trocino, IC Design Manager, Coherent Logix "thanks for efficient tools which have been successfully used in our internal wireless design flow. Friendly support has been highly appreciated." -Claudine Raibaut,EDA Manager, Texas Instruments "Baya is a mature production quality tool with features and capabilities beyond those of tools provided by large EDA vendors. It's flexibility is a key reason we have chosen it for use in our Cloud-based platform." -David Fritz, CEO, Social Silicon "Kanai produced an excellent tool set, which is very useful for a complex system-on-chip integration flows. We were skeptical in the beginning, but later got really impressed by a high quality and ease of use. Bridgit IPXACT creator helps us to pack register, bus and module interfaces into a IEEE standard *.xml SPIRIT format to ensure high reusability in the future and protect our investments. I high recommend using Kanai’s products for every system-on-chip manufacturer and invest Venture Capital to support further improvement and commercialization." -Boris V. Kuznetsov Processorpreneur, CEO @ SOCC "Hi Kanai, thanks a lot for creating DesignPlayer and the huge java class lib behind. Even I discoverd only the tip of the iceberg, I got already a lot of my project done. I'm sure there is much more. Your strong support makes me confident to explore more details in future." -Rolf Kemper, Manager, Mixed Signal Design, Renesas Electronics Europe "We were very pleased with your response. The VHDL2Verilog translator worked great, even handling the generate statements in the source VHDL. It met our needs exactly. It was very easy to work with you and you delivered the translator super fast. Thanks for the great support!" -Jerry Frenkil, VP of Engineering, NanoWatt Design "EDAUtils is one (if not the only one) of the most comprehensive tools for SoC design and integration and it is available for free. I included EDAUtils in the latest OpenTech Package as featured application among all free open source designs and tools and I believe with a lot of efforts it will grow to be one of the major tools in this domain."- Jamil Khatib, OpenTech Package
Verilog Preprocessor