Baya- SoC Intgration Platform, IP-XACT 1685, Translators and Converters
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EDAUtils provides a comprehensive SoC Integration Platform, named Baya, to assemble IPs defined in IP-XACT, Verilog or VHDL. Baya offers an excellent GUI with Commands, Tool Boxes and Connection Wizard to import IPs, instantiate components and build connection among the same. Baya  comes with a very rich set of Tcl commands- there are around 200 high level Tcl commands and hundreds of low level APIs for the advanced users. 
If you have any question concerning bug fixes, new features and  enhancements, please don't hesitate to contact. You will get the best solutions at the earliest.
Salient Features of Baya
Over the past few years, the consumer revolution has led to a convergence of applications on a single device and this trend is continuing with the growing market of smartphones where the target is enable the consumers to read e-mail, text friends, create spreadsheets and documents, watch YouTube, play video games, listen to music, take pictures, store them, get directions. To meet this growing consumer demad, today we have SoCs that contain hundreds of IP blocks and cores that can come from other departments, other divisions or even bought as commercial IP and integrating these IPs requres strong SoC Integration solution. 
Baya GUI

  • Comes with 200+ high level Tcl commands around SoC platform assembly

  • Easy to get started

    • Use the verilog2baya tool to convert existing SoC/SS into Baya

  • Supports Adhoc and Interface based connections

  • Supports Autoconnections

    • Rule based connections between component ports

  • Maintains a connectivity database with advance queries

    • What are the instances that a specific instance is connected with

    • What are the connections between any two instances

  • Supports a variety of SoC integration Methodologies

    • XLS/CSV Based connections

    • Port-to-Port Adhoc connections

    • IP-XACT and System Verilog Interface based connections

  • Hierarchy Manipulation to create Power Domain, Voltage Domain, comply with Floor planning

    • Insert new hierarchy

    • Remove existing hierarchy

  • Associate the IP-XACT memory maps with the SoC component instances

    • Dump out the C Model for the entire design

  • Supports Glue-Logic insertion

  • Spare port insertion through hierarchies

  • Supports automatic creation of the top module and it's ports based upon specified rule

  • Creates empty module corresponding to the instances

    • Use these empty modules to compile and elaborate the top for Lint checking

  • Utility to compare Entities, Modules and IP-XACT Components

    • Required to assess the impact on connectivity whenever there is new release

  • IP-XACT Coherency checker

    • To ensure the compliance of IP-XACT with respective Module/Entity

  • Tcl command to save the database as VHDL, Verilog and IP-XACT Design

  • Reports Design Maturity in terms of % of unconnected ports

  • Unix like commands( e.g. ls, cd, rename etc. ) to browse the design

  • Powerful GUI

    • Displays components from the IP-XACT Library and Verilog

    • Displays the associated bus interfaces in a component

    • Hierarchical view of Registers and BitFields.

    • Easy way to capture connectivity intent.

    • Drag an drop modules from the library to instantiate

The collection of tools and utilities fills a real void in EDA. The baya tool is exactly what we had been looking for to assemble large top-level modules in Verilog. The GUI and high-level TCL commands are intuitive, allowing designers to get started immediately and feel right at home. It was straightforward to quickly reproduce a module previously done with a Perl-to-Verilog utility that was hard to use and maintain. The support from Kanai is excellent. He responds quickly and is a pleasure to deal with. Nice work, Kanai!”-Michael Trocino, IC Design Manager, Coherent Logix "thanks for efficient tools which have been successfully used in our internal wireless design flow. Friendly support has been highly appreciated." -Claudine Raibaut,EDA Manager, Texas Instruments "Baya is a mature production quality tool with features and capabilities beyond those of tools provided by large EDA vendors. It's flexibility is a key reason we have chosen it for use in our Cloud-based platform." -David Fritz, CEO, Social Silicon "Kanai produced an excellent tool set, which is very useful for a complex system-on-chip integration flows. We were skeptical in the beginning, but later got really impressed by a high quality and ease of use. Bridgit IPXACT creator helps us to pack register, bus and module interfaces into a IEEE standard *.xml SPIRIT format to ensure high reusability in the future and protect our investments. I high recommend using Kanai’s products for every system-on-chip manufacturer and invest Venture Capital to support further improvement and commercialization." -Boris V. Kuznetsov Processorpreneur, CEO @ SOCC "Hi Kanai, thanks a lot for creating DesignPlayer and the huge java class lib behind. Even I discoverd only the tip of the iceberg, I got already a lot of my project done. I'm sure there is much more. Your strong support makes me confident to explore more details in future." -Rolf Kemper, Manager, Mixed Signal Design, Renesas Electronics Europe "We were very pleased with your response. The VHDL2Verilog translator worked great, even handling the generate statements in the source VHDL. It met our needs exactly. It was very easy to work with you and you delivered the translator super fast. Thanks for the great support!" -Jerry Frenkil, VP of Engineering, NanoWatt Design "EDAUtils is one (if not the only one) of the most comprehensive tools for SoC design and integration and it is available for free. I included EDAUtils in the latest OpenTech Package as featured application among all free open source designs and tools and I believe with a lot of efforts it will grow to be one of the major tools in this domain."- Jamil Khatib, OpenTech Package