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Verilog to SystemC Translator
If you have any question concerning bug fixes, new features and  enhancements, please don't hesitate to contact. You will get the best solutions at the earliest.
        This utility has been developed for those who wants to convert an existing verilog design into SystemC. Such translation is required to mdel an existing IPs after re-architecting the same. This has been developed in Java( 1.6.x ) in order to make it platform independent and bundled as an executable JAR file.


        source setup_env.('csh' or 'sh' or 'bat' as applicable )
        verilog2systemc -in simple_and.v -top simple_and -outdir outputdir
        java com.eu.miscedautils.verilog2sc.verilog2systemc -f vlog_files.list -top mytopmodulename +define+directive1 +incdir+inc1+inc2 -outdir tmpdir

     Use the switch -two_value_logic in case you want to translate the design in the 2 value logic( '0' and '1' ) based SystemC.

     You can provide verilog files in any order even as *.v ( inside the lits file ) and use the -sort switch to sort them internally before processing them.

     It generates a Makefile in the output directory in order to compile the generated files in the right order and to link them to build the executable. 

Get all the options by executing it as 'verilog2systemc -help
Send your feedback to help@edautils.com for  further improvement of this tool.