Baya- AI Enabled SoC Intgration Platform, IP-XACT 1685, UPF, Verilog and VHDL Parsers, Translators & Converters, Datamodel and Re-Writers
Home
Run Online
Download
Online Demo
Tutorial Online
FAQ
Contact Us

Baya - Auto Integration of SoC Components with IP-XACT & Tcl API
If you have any question concerning bug fixes, new features and  enhancements, please don't hesitate to contact. You will get the best solutions at the earliest.
          This tool generates Verilog testbench with random stimuli. User can specify clocks and resets with waveforms and optionally associates ports with the same. It also generates modelim and ncsim compilation & simulation scripts.

How to run this tool ?
      Download and extract the tar file and follow the simple steps/commands to generate the testbench. There are few examples which can be used as reference. Here is one example--

 source setup_env.('csh' or 'sh' or 'bat' as applicable )

 Alternatively, for Unix
 setenv EDAUTILS_ROOT /usr/user1/DesignPlayer-linux.x86/01MAY2014 ( installation dir )
 set path = ( $EDAUTILS_ROOT/bin $path )

 and for Windows
 set EDAUTILS_ROOT=D:\tmp\DesignPlayer-win32.x86_64\01MAY2014 ( installation dir )
 set PATH="%path%;%EDAUTILS_ROOT%\bin"
 
 gentbvlog -in simple_and.v -top simple_and -out tb.v [+incdir+dir1+dir2] [-clk "clock1@10{data:address}" -clk clk2] [-rst reset1 -rst reset2]

                                OR

    java com.eu.miscedautils.gentbvlog.GenTBVlog  -in simple_and.v -top simple_and -out tb.v [+incdir+dir1+dir2] [-clk clock1] [-rst reset1]
% gentbvlog -in include_header.v +incdir+include1+include2 -top include_header -out tb.v 
  
                    Simulation with Modesim
%vlib work

%vmap work work

%vlog include_header.v +incdir+include1+include2

% vlog tb.v

%vsim -c -lib work testbench < run.do
....
....

VSIM 1> run -all
#                    0 in1 = xx , in2 = xxxxxx , out1 = 00xx
#                    5 in1 = 00 , in2 = 100100 , out1 = 0000
#                   10 in1 = 10 , in2 = 000001 , out1 = 0000
#                   15 in1 = 00 , in2 = 001001 , out1 = 0000
#                   20 in1 = 01 , in2 = 100011 , out1 = 0001
#                   25 in1 = 00 , in2 = 001101 , out1 = 0000
#                   30 in1 = 10 , in2 = 001101 , out1 = 0000
#                   35 in1 = 01 , in2 = 100101 , out1 = 0001
.....
.....
#                  195 in1 = 00 , in2 = 001101 , out1 = 0000
# ** Note: $finish    : tb.v(30)
#    Time: 200 ns  Iteration: 0  Instance: /testbench

Generated Verilog Testbench: tb.v

//////////////////////////////////////////////////////////////////////////////////////////////////////
//                                                                                                  //
// This testbench has been generated by the Verilog                 //
// testbench generator.                                                                //
// Copyright (C) 2012  edautils.com.                                           //
// Contact help@edautils.com  for support/info.                        //
//                                                                                                 //
//                                                                                                 //
/////////////////////////////////////////////////////////////////////////////////////////////////////
//
//
// Generated by : Ron  on 5/23/10 9:10 PM
//
//
module testbench;
reg [0:7] indata_array;
wire  [3:0] tmp_out1;
include_header inst(.in1(indata_array[0:1]), .in2(indata_array[2:7]), .out1(tmp_out1));
always
begin
#5  indata_array = $random;
end
initial
begin
$monitor($time, " in1 = %b , in2 = %b , out1 = %b  ",
indata_array[0:1], indata_array[2:7], tmp_out1);
end
initial
begin
#200 $finish;
end
endmodule

The collection of tools and utilities fills a real void in EDA. The baya tool is exactly what we had been looking for to assemble large top-level modules in Verilog. The GUI and high-level TCL commands are intuitive, allowing designers to get started immediately and feel right at home. It was straightforward to quickly reproduce a module previously done with a Perl-to-Verilog utility that was hard to use and maintain. The support from Kanai is excellent. He responds quickly and is a pleasure to deal with. Nice work, Kanai!”-Michael Trocino, IC Design Manager, Coherent Logix "thanks for efficient tools which have been successfully used in our internal wireless design flow. Friendly support has been highly appreciated." -Claudine Raibaut,EDA Manager, Texas Instruments "Baya is a mature production quality tool with features and capabilities beyond those of tools provided by large EDA vendors. It's flexibility is a key reason we have chosen it for use in our Cloud-based platform." -David Fritz, CEO, Social Silicon "Kanai produced an excellent tool set, which is very useful for a complex system-on-chip integration flows. We were skeptical in the beginning, but later got really impressed by a high quality and ease of use. Bridgit IPXACT creator helps us to pack register, bus and module interfaces into a IEEE standard *.xml SPIRIT format to ensure high reusability in the future and protect our investments. I high recommend using Kanai’s products for every system-on-chip manufacturer and invest Venture Capital to support further improvement and commercialization." -Boris V. Kuznetsov Processorpreneur, CEO @ SOCC "Hi Kanai, thanks a lot for creating DesignPlayer and the huge java class lib behind. Even I discoverd only the tip of the iceberg, I got already a lot of my project done. I'm sure there is much more. Your strong support makes me confident to explore more details in future." -Rolf Kemper, Manager, Mixed Signal Design, Renesas Electronics Europe "We were very pleased with your response. The VHDL2Verilog translator worked great, even handling the generate statements in the source VHDL. It met our needs exactly. It was very easy to work with you and you delivered the translator super fast. Thanks for the great support!" -Jerry Frenkil, VP of Engineering, NanoWatt Design "EDAUtils is one (if not the only one) of the most comprehensive tools for SoC design and integration and it is available for free. I included EDAUtils in the latest OpenTech Package as featured application among all free open source designs and tools and I believe with a lot of efforts it will grow to be one of the major tools in this domain."- Jamil Khatib, OpenTech Package
Verilog Testbench Generator