Baya - Auto Integration of SoC Components with IP-XACT & Tcl API
This utility has been developed for those who wants to generate IP-XACT Component or Design from an existing verilog design. In order to generate IP-XACT Design from Verilog, user will have to provide the definition of the Components instantiated in the Verilog or provide correct search path to the Component library. This has been developed in Java( 1.6.x ) in order to make it platform independent and bundled as an executable JAR file.
Usage:
source setup_env.('csh' or 'sh' or 'bat' as applicable )
Alternatively, for Unix
setenv EDAUTILS_ROOT /usr/user1/DesignPlayer-linux.x86/01MAY2014 ( installation dir )
set path = ( $EDAUTILS_ROOT/bin $path )
and for Windows
set EDAUTILS_ROOT=D:\tmp\DesignPlayer-win32.x86_64\01MAY2014 ( installation dir )