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Miscellaneous EDA Utilities
Verilog to VHDL Converter
If you have any question concerning bug fixes, new features and  enhancements, please don't hesitate to contact. You will get the best solutions at the earliest.
        This utility has been developed for those who wants to convert an existing verilog design into VHDL. The generated VHDL may not work as is and may require minor manual correction in order to ensure the VHDL data type matching. This has been developed in Java( 1.6.x ) in order to make it platform independent and bundled as an executable JAR file.


        source setup_env.('csh' or 'sh' or 'bat' as applicable )
        verilog2vhdl -in simple_and.v -top simple_and_top -out simple_and.vhd

         java com.eu.miscedautils.verilog2vhdl.verilog2vhdl -in simple_and.v -top simple_and -out output.vhd

You can provide multple verilog files even with wildcard like *.v throught the -filelist switch. You can use the -sort switch to tell the tool to sort the files before processing them, this -sort switch is mandatory if your input files are in random order. Also, you can exclude files with the -excludefilelist switch which also supports wildcards

There are other switches like -only_entity to create just the entity correspomding to the specified top. Similarly, there is -only_component to create a component declaration corresponding to the specified module.

This output VHDL file is dependent on the following two files which are part of this tool's tar ball-


This is how you can compile and simulate the generated VHDL the modelsim simulator-

       vlib misc
       vlib vl2vh_work
       vmap misc misc
       vmap vl2vh_work vl2vh_work
       vcom -work misc $EDAUTILS_ROOT/vhdl_pkgs/src/misc/misc.vhd 
       vcom -work misc 
       vcom -work vl2vh_work simple_and.vhd
       vsim -c -lib vl2vh_work simple_and_top

Get details by executing it as 'verilog2vhdl -help
Send your feedback to help@edautils.com for  further improvement of this tool.

Known Limitations:
      1) This tools assumes that the parameters are of INTEGER type and not of type string. It blindly defines those as integer and initializes the same by converting the verilog values into INTEGER.  It may require manual intervention to rectify this. 
      2) The expressions type in the 'IF' condition, '=' and '/=' operator, assignment will require intervention since VHDL is strongly typed.
      3) Some verilog predefined primitivies are not supported, e.g. transif0, transif1, trans .
      4) System Verilog is not supported. Only limited construct in Verilog-2K is supported

Relevant files

See Also  vhdl2verilog