Baya- SoC Intgration Platform, IP-XACT 1685, Translators and Converters
Home
Online Demo
Tutorial Online
FAQ
Contact Us
LICENSE

Introduced Live Support, use chat box in the bottom-right to talk to us
If you have any question concerning bug fixes, new features and  enhancements, please don't hesitate to contact. You will get the best solutions at the earliest.
        This utility has been developed for those who wants to convert an existing verilog design into VHDL. The generated VHDL may not work as is and may require minor manual correction in order to ensure the VHDL data type matching. This has been developed in Java( 1.6.x ) in order to make it platform independent and bundled as an executable JAR file.

Usage:

        source setup_env.('csh' or 'sh' or 'bat' as applicable )

        Alternatively, for Unix
        setenv EDAUTILS_ROOT /usr/user1/DesignPlayer-linux.x86/01MAY2014 ( installation dir )
        set path = ( $EDAUTILS_ROOT/bin $path )

        and for Windows

        set EDAUTILS_ROOT=D:\tmp\DesignPlayer-win32.x86_64\01MAY2014 ( installation dir )
        set PATH="%path%;%EDAUTILS_ROOT%\bin"

        verilog2vhdl -in simple_and.v -top simple_and_top -out simple_and.vhd

                                 OR
         java com.eu.miscedautils.verilog2vhdl.verilog2vhdl -in simple_and.v -top simple_and -out output.vhd

You can provide multple verilog files even with wildcard like *.v throught the -filelist switch. You can use the -sort switch to tell the tool to sort the files before processing them, this -sort switch is mandatory if your input files are in random order. Also, you can exclude files with the -excludefilelist switch which also supports wildcards

There are other switches like -only_entity to create just the entity correspomding to the specified top. Similarly, there is -only_component to create a component declaration corresponding to the specified module.

This output VHDL file is dependent on the following two files which are part of this tool's tar ball-

$EDAUTILS_ROOT/vhdl_pkgs/src/misc/misc.vhd 
$EDAUTILS_ROOT/vhdl_pkgs/src/misc/vl2vh_primitives.vhd

This is how you can compile and simulate the generated VHDL the modelsim simulator-

       vlib misc
       vlib vl2vh_work
       vmap misc misc
       vmap vl2vh_work vl2vh_work
       vcom -work misc $EDAUTILS_ROOT/vhdl_pkgs/src/misc/misc.vhd 
       vcom -work misc 
$EDAUTILS_ROOT/vhdl_pkgs/src/misc/vl2vh_primitives.vhd
       vcom -work vl2vh_work simple_and.vhd
       vsim -c -lib vl2vh_work simple_and_top


Get details by executing it as 'verilog2vhdl -help
Send your feedback to help@edautils.com for  further improvement of this tool.

Known Limitations:
      1) This tools assumes that the parameters are of INTEGER type and not of type string. It blindly defines those as integer and initializes the same by converting the verilog values into INTEGER.  It may require manual intervention to rectify this. 
      2) The expressions type in the 'IF' condition, '=' and '/=' operator, assignment will require intervention since VHDL is strongly typed.
      3) Some verilog predefined primitivies are not supported, e.g. transif0, transif1, trans .
      4) System Verilog is not supported. Only limited construct in Verilog-2K is supported
Download

Relevant files
      vl2vh_primitives.vhd
      misc.vhd
      cells.vhd

See Also  vhdl2verilog
The collection of tools and utilities fills a real void in EDA. The baya tool is exactly what we had been looking for to assemble large top-level modules in Verilog. The GUI and high-level TCL commands are intuitive, allowing designers to get started immediately and feel right at home. It was straightforward to quickly reproduce a module previously done with a Perl-to-Verilog utility that was hard to use and maintain. The support from Kanai is excellent. He responds quickly and is a pleasure to deal with. Nice work, Kanai!”-Michael Trocino, IC Design Manager, Coherent Logix "thanks for efficient tools which have been successfully used in our internal wireless design flow. Friendly support has been highly appreciated." -Claudine Raibaut,EDA Manager, Texas Instruments "Baya is a mature production quality tool with features and capabilities beyond those of tools provided by large EDA vendors. It's flexibility is a key reason we have chosen it for use in our Cloud-based platform." -David Fritz, CEO, Social Silicon "Kanai produced an excellent tool set, which is very useful for a complex system-on-chip integration flows. We were skeptical in the beginning, but later got really impressed by a high quality and ease of use. Bridgit IPXACT creator helps us to pack register, bus and module interfaces into a IEEE standard *.xml SPIRIT format to ensure high reusability in the future and protect our investments. I high recommend using Kanai’s products for every system-on-chip manufacturer and invest Venture Capital to support further improvement and commercialization." -Boris V. Kuznetsov Processorpreneur, CEO @ SOCC "Hi Kanai, thanks a lot for creating DesignPlayer and the huge java class lib behind. Even I discoverd only the tip of the iceberg, I got already a lot of my project done. I'm sure there is much more. Your strong support makes me confident to explore more details in future." -Rolf Kemper, Manager, Mixed Signal Design, Renesas Electronics Europe "We were very pleased with your response. The VHDL2Verilog translator worked great, even handling the generate statements in the source VHDL. It met our needs exactly. It was very easy to work with you and you delivered the translator super fast. Thanks for the great support!" -Jerry Frenkil, VP of Engineering, NanoWatt Design "EDAUtils is one (if not the only one) of the most comprehensive tools for SoC design and integration and it is available for free. I included EDAUtils in the latest OpenTech Package as featured application among all free open source designs and tools and I believe with a lot of efforts it will grow to be one of the major tools in this domain."- Jamil Khatib, OpenTech Package
System Verilog To VHDL Translator