Tool Category

Tool Name

Short Description

Download Link

DesignPlayer

DesignPlayer GUI

Contains all the EDAUtils' tools in commandline mode and also the GUI.

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designplayer-shell

Collection of all EDAUtils'capabilities in the commandline mode.

Baya

baya-shell

SoC integration solution and associated utilities required for the IP assembly.

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compareentities

Compare VHDL Entities especially to check if there is any change port or generics. Mostly used to compare same entity's two release versions.

comparemoduleinterfaces

Compare port and parameter changes between two verilog modules. It is often used to assess integration effort impact when a an IP is released to SOC.

createhierarchy

Utility to group instances selectively to build a new Tile/Partition in the SOC.

removehierarchy

Removes Verilog RTL hierarchies as specified by the users.

flatteninstances

Flatten selective hierarchies in the SOC keeping the RTL intent intact.

flattenverilog

Utility to flatten all RTL hierarchies in a module keeping the design intent intact.

gendocverilog

Utility to generate IP documentation from the Verilog definition.

genregisterdochtml

Generate HTML documentation from the IP-XACT Register file.

genregistercmodel

Generate C model from the IP-XACT Register definition.

genregisteruvmmodel

Utility to generate UVM model from the IP-XACT Register File.

genwrapperverilog

Generate Verilog wrapper with simple Verilog-95 ports and parameters on of a SV Verilog module with complex ports and parameters by flattening those.

Also, generates wrapper on top of a VHDL entity.

genwrappervhdl

Generates VHDL wrapper on top of a Verilog module or VHDL entity.

IP-XACT

IP-XACT GUI to create/modify

GUI Tool(s) to create IP-XACT files from scratch or update existing ones

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ipxact-shell

Collection of all the IP-XACT related utilities from EDAUtils.

verilog2ipxact

Generate IP-XACT Component definition from Verilog module definition.

vhdl2ipxact

Utility to generate IP-XACT component definition from a VHD entity.

xls2ipxact

Convert XLS based register definition into IP-XACT Register.

ipxact2tlm

Generates TLM model from the IP-XACT defition.

ipxact2verilog

Generate Verilog module from the IP-XACT definition

ipxact2vhdlentity

Generate VHDL entity from the IP-XACT Component definition.

genregisterdochtml

Generate HTML documentation from the IP-XACT Register file.

genregistercmodel

Generate C model from the IP-XACT Register definition.

genregisteruvmmodel

Utility to generate UVM model from the IP-XACT Register File.

ipxactcoherencychecker

Utility to check consistency between IP-XACT Component and Verilog/VHDL implementation of an IP.

ipxactinterface2svinterface

Generate SV interface from the IP-XACT interface( Bus/Abstraction ) definitions.

ipxactreg2verilog

Generate Verilog definition from the IP-XACT register definition.

ipxactreg2xlsreg

Create REGISTER XLS by translating the IP-XACT register definition details.

validateipxact – IP-XACT Linting

IP-XACT Linting solution – checks syntax/semantics of IP-XACT component and Register definition.

upgradeipxact

IP-XACT older version to newer version migration.

RTL Utilities

sdc-shell

Utility to read SDC file and print out effective commands by resolving Tcl procs, variables etc.

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upf-shell

UPF parser implemented in Java. Also, utility to read UPF commands buried inside Tcl procs and vriables/equations and it decompiles the effective commands.

parseliberty

Liberty .lib parser implemented in Java. Tool developer can use this parser to build relevant application involving .lib reading.

parsevcd

VCD parser implemented in Java.

parseverilog

SystemVerilog parser with Java API

parsevhdl

VHDL parser with Java API

preprocessverilog

Utility to preprocess SystemVerilog file by resolving compiler directives(macro e.g. `define/ìfdef/...).

punchports

Utility to insert a new pin deep in RTL hierarchy and pull that out to the top by inserting pins in the necessary hierarchical paths.

mergemodules

Solution to pull instances( read HMs/Tiles ) from two SoC/HMs and build a new HM/Tile to maximize the reuse across SOCs. Additional details.

swapcells

Swaps verilog module, library cells, memories with another definition of the same

uniquifyverilog

Uniquify SystemVerilog modules, classes, structures, interfaces and packages and their usages in the given IP.

removeassignments

Remove intermediate assignment statements in the Verilog module RTL.

verilog2lib

Create .lib file from the Verilog definition of a module/IP.

verilog2systemc

Generate SystemC definition of an IP from its existing Verilog implementation. It is useful when an IP is planned for re-implement/re-architecture. The generated output requires fie tuning since it is not 100% correct.

verilog2vhdl

Verilog to VHDL converter

vhdl2systemc

Utility to convert VHDL definition of an IP into SystemC. There generated SC will require manual refinement.

vhdl2verilog

Verilog to VHDL converter utility.

lib2verilog

Generate verilog mdoule(s) from the Liberty .lib file.

vhdltbgen

Simple testbench generator utility in VHDL.

vlogtbgen

Simple testbench generator utility in Verilog.