Comes with 200+ high level Tcl commands around SoC platform assembly
Easy to get started
Use the verilog2baya tool to convert existing SoC/SS into Baya
Supports Adhoc and Interface based connections
Supports Autoconnections
Rule based connections between component ports
Maintains a connectivity database with advance queries
What are the instances that a specific instance is connected with
What are the connections between any two instances
Supports a variety of SoC integration Methodologies
XLS/CSV Based connections
Port-to-Port Adhoc connections
IP-XACT and System Verilog Interface based connections
Hierarchy Manipulation to create Power Domain, Voltage Domain, comply with Floor planning
Insert new hierarchy
Remove existing hierarchy
Associate the IP-XACT memory maps with the SoC component instances
Dump out the C Model for the entire design
Supports Glue-Logic insertion
Spare port insertion through hierarchies
Supports automatic creation of the top module and it's ports based upon specified rule
Creates empty module corresponding to the instances
Use these empty modules to compile and elaborate the top for Lint checking
Utility to compare Entities, Modules and IP-XACT Components
Required to assess the impact on connectivity whenever there is new release
IP-XACT Coherency checker
To ensure the compliance of IP-XACT with respective Module/Entity
Tcl command to save the database as VHDL, Verilog and IP-XACT Design
Reports Design Maturity in terms of % of unconnected ports
Unix like commands( e.g. ls, cd, rename etc. ) to browse the design
Powerful GUI
Displays components from the IP-XACT Library and Verilog
Displays the associated bus interfaces in a component
Hierarchical view of Registers and BitFields.
Easy way to capture connectivity intent.
Drag an drop modules from the library to instantiate