This tool reads Verilog design and ungroups the specified list of instances and finally dumps out the modified design. You may also consider to explore the flatteninstances tool to flatten specific hierarchical instances. This utility been developed in Java( 1.6.x ) in order to make it platform independent and bundled as an executable JAR file which can be directly used from the 'lib' directory in the downloaded tar or ZIP file. Example-
source setup_env.('csh' or 'sh' or 'bat' as applicable )
Alternatively, for Unix
setenv EDAUTILS_ROOT /usr/user1/DesignPlayer-linux.x86/01MAY2014 ( installation dir )
set path = ( $EDAUTILS_ROOT/bin $path )
and for Windows
set EDAUTILS_ROOT=D:\tmp\DesignPlayer-win32.x86_64\01MAY2014 ( installation dir )
Go through the examples to get a better understanding of this tool. The examples are pretty comprehensive and covers wide range of possible scenario. Send mails to firstname.lastname@example.org if you need any assistance.
Get details by executing it as 'removehierarchy -help'
System Verilog RTL Hierarchy Removal/Ungroup Utility