This utility prints clock and reset trees in a given netlist. This utility has been implemented as Tcl command in the DesignPlayer Shell and it works for any scalar nets instead of just the clock and reset. Follow the below command after installing the tar/zip file-
source setup_env.('csh' or 'sh' or 'bat' as applicable )
cd examples/brigid-shell/clock_reset_tree_1
brigid-shell
brigid >brigid_read_verilog -file i2c_netlist.v
brigid >set mod [ brigid_verilog_find_module -name i2c ]
brigid >$mod link
brigid >$mod elaborate
brigid >set fo [ brigid_print_clock_reset_tree -module i2c -from clk -buffers _BUF -to cellNone -exact -nonets ]
######## Printing clock/reset tree paths ##############
i2c/clkbuf_level_1/clkin(CLK_BUF)
->hierarchical_fanout/mid_inst/leaf_inst1/clkbuf_leaf1/clkin(CLK_BUF)
->hierarchical_fanout/mid_inst/leaf_inst1/clkout(wire)
i2c/clkbuf_level_1/clkin(CLK_BUF)
->hierarchical_fanout/mid_inst/leaf_inst2/clkbuf_leaf1/clkin(CLK_BUF)
->hierarchical_fanout/mid_inst/leaf_inst2/clkout(wire)
######## End printing clock/reset tree paths ##############
brigid >
Command: brigid_print_clock_reset_tree
Description: Prints the list of clock/reset tree starting from the
given clock/reset netname in the specified module until
it hits the given endpoint. The endpoints are nothing
but the list of library cells which are not part of the
clock/reset tree path.
Options :
-module , mandatory input to specify the module
name from where the clock tree starts
-from , mandatory input to specify the
root clock or reset name from where
path needs to be traced.
-to , mandatory input to provide the list
of library cells separated with
colon(:) which are not part of the
clock/reset tree. This input is
required in order to find the end of
of the tree path. Generally it will
be flip-flops ...
-buffers , mandatory input to provide the
list of library cells separated with
colon(:) which are part of the
clock/reset tree. The clock/reset
buffers, ICG and some mux may be
part of this argument.
-nonets , optional input to specify if the intermediate
nets to be ignored. Default, its false
-noformat , optional input to disable formattting of the output
-exact , optional input to specify if the given clock/reset
names are exact full names i.e. skip
pattern matching in clock/rst names
Returns : The list of clock/reset tree paths. Prints the same.
Example : brigid_print_clock_reset_tree -module top_module -from clk -to ff1:ff2 -buffers ctb:icg1:mux2 -nonets
Output:
######## Printing clock/reset tree paths ##############
simple_fanout/clk(wire)
->simple_fanout/clkbuf_level_1/clkin(CLK_BUF)
->simple_fanout/w_1(wire)
->simple_fanout/clkbuf_level_2/clkin(ctbuf_2)
->simple_fanout/w_2_1(wire)
->simple_fanout/clkbuf_level_3/clkin(CLK_BUF)
->simple_fanout/w_2_2(wire)
simple_fanout/clk(wire)
->simple_fanout/clkbuf_level_1/clkin(CLK_BUF)
->simple_fanout/w_1(wire)
->simple_fanout/clkbuf_level_2/clkin(ctbuf_2)
->simple_fanout/w_2_1(wire)
->simple_fanout/clkbuf_level_4/clkin(ctbuf_2)
->simple_fanout/w_2_3(wire)
######## End printing clock/reset tree paths ##############
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