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    This utility prints clock and reset trees in a given netlist. This utility has been implemented as Tcl command in the DesignPlayer Shell and it works for any scalar nets instead of just the clock and reset. Follow the below command after installing the tar/zip file-

      source setup_env.('csh' or 'sh' or 'bat' as applicable )
      cd examples/brigid-shell/clock_reset_tree_1
      brigid >brigid_read_verilog -file i2c_netlist.v
      brigid >set mod [ brigid_verilog_find_module -name i2c ]
      brigid >$mod link
      brigid >$mod elaborate
      brigid >set fo [ brigid_print_clock_reset_tree -module  i2c -from clk -buffers _BUF -to cellNone -exact -nonets ]
      ######## Printing clock/reset tree paths ##############
      ######## End printing clock/reset tree paths ##############
      brigid >

Description: Prints the list of clock/reset tree starting from the 
given clock/reset netname in the specified module until
 it hits the given endpoint. The endpoints are nothing
 but the list of library cells which are not part of the
 clock/reset tree path.
Options :
-module , mandatory input to specify the module
 name from where the clock tree starts
-from , mandatory input to specify the
 root clock or reset name from where
 path needs to be traced. 
-to , mandatory input to provide the list
 of library cells separated with
 colon(:) which are not part of the
 clock/reset tree. This input is
 required in order to find the end of
 of the tree path. Generally it will
 be flip-flops ...
-buffers , mandatory input to provide the
 list of library cells separated with
 colon(:) which are part of the
 clock/reset tree. The clock/reset
buffers, ICG and some mux may be
 part of this argument.
-nonets , optional input to specify if the intermediate
 nets to be ignored. Default, its false
-noformat , optional input to disable formattting of the output
-exact , optional input to specify if the given clock/reset
 names are exact full names i.e. skip
 pattern matching in clock/rst names
Returns : The list of clock/reset tree paths. Prints the same.
Example : brigid_print_clock_reset_tree -module top_module -from clk -to ff1:ff2 -buffers ctb:icg1:mux2 -nonets


######## Printing clock/reset tree paths ##############
######## End printing clock/reset tree paths ##############

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The collection of tools and utilities fills a real void in EDA. The baya tool is exactly what we had been looking for to assemble large top-level modules in Verilog. The GUI and high-level TCL commands are intuitive, allowing designers to get started immediately and feel right at home. It was straightforward to quickly reproduce a module previously done with a Perl-to-Verilog utility that was hard to use and maintain. The support from Kanai is excellent. He responds quickly and is a pleasure to deal with. Nice work, Kanai!”-Michael Trocino, IC Design Manager, Coherent Logix "thanks for efficient tools which have been successfully used in our internal wireless design flow. Friendly support has been highly appreciated." -Claudine Raibaut,EDA Manager, Texas Instruments "Baya is a mature production quality tool with features and capabilities beyond those of tools provided by large EDA vendors. It's flexibility is a key reason we have chosen it for use in our Cloud-based platform." -David Fritz, CEO, Social Silicon "Kanai produced an excellent tool set, which is very useful for a complex system-on-chip integration flows. We were skeptical in the beginning, but later got really impressed by a high quality and ease of use. Bridgit IPXACT creator helps us to pack register, bus and module interfaces into a IEEE standard *.xml SPIRIT format to ensure high reusability in the future and protect our investments. I high recommend using Kanai’s products for every system-on-chip manufacturer and invest Venture Capital to support further improvement and commercialization." -Boris V. Kuznetsov Processorpreneur, CEO @ SOCC "Hi Kanai, thanks a lot for creating DesignPlayer and the huge java class lib behind. Even I discoverd only the tip of the iceberg, I got already a lot of my project done. I'm sure there is much more. Your strong support makes me confident to explore more details in future." -Rolf Kemper, Manager, Mixed Signal Design, Renesas Electronics Europe "We were very pleased with your response. The VHDL2Verilog translator worked great, even handling the generate statements in the source VHDL. It met our needs exactly. It was very easy to work with you and you delivered the translator super fast. Thanks for the great support!" -Jerry Frenkil, VP of Engineering, NanoWatt Design "EDAUtils is one (if not the only one) of the most comprehensive tools for SoC design and integration and it is available for free. I included EDAUtils in the latest OpenTech Package as featured application among all free open source designs and tools and I believe with a lot of efforts it will grow to be one of the major tools in this domain."- Jamil Khatib, OpenTech Package
Clock, Reset and Any Scalar Signal Tracer in Verilog Netlist and Structural Design