Baya- AI Enabled SoC Intgration Platform, IP-XACT 1685, UPF, Verilog and VHDL Parsers, Translators & Converters, Datamodel and Re-Writers
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Baya - Auto Integration of SoC Components with IP-XACT & Tcl API
If you have any question concerning bug fixes, new features and  enhancements, please don't hesitate to contact. You will get the best solutions at the earliest.
    This utility has been aimed for those designers who do not know the dependency of the VHDL / Verilog files in a given design nor they know which file to compile in which work library. This platform independent utility takes all the RTL files as input and then process those files internally and come up with a sorted/ordered list of files along with their proper VHDL /Verilog work library. The sorted output is written in the file sorted.out.list . It also creates modelsim and compilation scripts along with library mappings. The generated sorted.out.list file can be used to create compilation script for any VHD/Verilog tool. To run this tool goto to the installation area and source or execute the file setup_env file to setup the environment and then run it as -

    source setup_env.('csh' or 'sh' or 'bat' as applicable )

    Alternatively, for Unix
    setenv EDAUTILS_ROOT /usr/user1/DesignPlayer-linux.x86/01MAY2014 ( installation dir )
    set path = ( $EDAUTILS_ROOT/bin $path )

    and for Windows

    set EDAUTILS_ROOT=D:\tmp\DesignPlayer-win32.x86_64\01MAY2014 ( installation dir )
    set PATH="%path%;%EDAUTILS_ROOT%\bin"

    sorthdlfiles -filelist infile.list
                                 OR
    java com.eu.miscedautils.SortHDL.SortHDL -filelist infile.list 


You can list files with wild card as *.v* . Also, you can exclude files with the -excludefilelist switch, see the examples. This tool not only supprts complex VHDL configuration and it also works fine even if the RTL has any syntax or semantic error(s).

See below one example command and output of this tool.

%  sorthdlfiles -filelist infile.list -outfile modelsim_compile.csh 
  
                   HDL Sort Utility  
   
...     
...
SortHDL: Note: Running with options :  -filelist infile.list 

SortHDL: Running with: -filelist infile.list


SortHDL: Note: Reading file : atom_config.vhd ...
SortHDL: Note: Reading input file atom_config.vhd ...
SortHDL: Note: Reading file : atom.vhd ...
SortHDL: Note: Reading input file atom.vhd ...
...
...
SortHDL: Note: Reading file : leaf.v ...
SortHDL: Readinf file  leaf.v ... 
SortHDL: Note: Reading file : grandleaf.v ...
SortHDL: Readinf file  grandleaf.v ...

SortHDL: Note: Sorting files as per their expected compilation order ... 
SortHDL: Note: Sorting is done ...
SortHDL: Sorted the HDL(s) successfully ...
SortHDL: Thank you for using this utility
SortHDL: Send your suggestion/feedback to help@edautils.com
SortHDL: Exiting ...
                 Output compile script

!/bin/csh -f

#########################################################
## This compile script has been generated with the free        #
## RTL sorting tool called SortHDL from edautils.com    #
## Contact helpt@edautils.com for any help/support #
##                                                             #
#########################################################



\mkdir -p OUTPUTDIR
set outdir=OUTPUTDIR
vlib dummylib
vmap dummylib $outdir/dummylib
vlib protonlib
vmap protonlib $outdir/protonlib
vlib packlib
vmap packlib $outdir/packlib
vlib neutronlib
vmap neutronlib $outdir/neutronlib
vlib WORK
vmap WORK $outdir/WORK
vlib vloglib
vmap vloglib $outdir/vloglib
vlib atomlib1
vmap atomlib1 $outdir/atomlib1


vcom  -work dummylib electron.vhd
vcom  -work protonlib proton_e.vhd
vcom  -work protonlib proton_rtl.vhd
vcom  -work packlib simplepackage_p.vhd
vcom  -work packlib simplepackage_body.vhd
vcom  -work neutronlib neutron.vhd
## Add +incdir+<path-of-include-dir> if required
vlog  -work WORK grandleaf.v
## Add +incdir+<path-of-include-dir> if required
vlog  -work vloglib leaf.v
vcom  -work atomlib1 atom.vhd
vcom  -work atomlib1 atom_config.vhd
vcom  -work WORK molecule.vhd
vcom  -work WORK molecule_cfg_block.vhd
vcom  -work WORK molecule_cfg.vhd

    Content of the input file
atom_config.vhd
atom.vhd
electron.vhd
molecule_cfg_block.vhd
molecule_cfg.vhd
molecule.vhd
neutron.vhd
proton_e.vhd
proton_rtl.vhd
leaf.v
grandleaf.v
simplepackage_body.vhd
simplepackage_p.vhd
The collection of tools and utilities fills a real void in EDA. The baya tool is exactly what we had been looking for to assemble large top-level modules in Verilog. The GUI and high-level TCL commands are intuitive, allowing designers to get started immediately and feel right at home. It was straightforward to quickly reproduce a module previously done with a Perl-to-Verilog utility that was hard to use and maintain. The support from Kanai is excellent. He responds quickly and is a pleasure to deal with. Nice work, Kanai!”-Michael Trocino, IC Design Manager, Coherent Logix "thanks for efficient tools which have been successfully used in our internal wireless design flow. Friendly support has been highly appreciated." -Claudine Raibaut,EDA Manager, Texas Instruments "Baya is a mature production quality tool with features and capabilities beyond those of tools provided by large EDA vendors. It's flexibility is a key reason we have chosen it for use in our Cloud-based platform." -David Fritz, CEO, Social Silicon "Kanai produced an excellent tool set, which is very useful for a complex system-on-chip integration flows. We were skeptical in the beginning, but later got really impressed by a high quality and ease of use. Bridgit IPXACT creator helps us to pack register, bus and module interfaces into a IEEE standard *.xml SPIRIT format to ensure high reusability in the future and protect our investments. I high recommend using Kanai’s products for every system-on-chip manufacturer and invest Venture Capital to support further improvement and commercialization." -Boris V. Kuznetsov Processorpreneur, CEO @ SOCC "Hi Kanai, thanks a lot for creating DesignPlayer and the huge java class lib behind. Even I discoverd only the tip of the iceberg, I got already a lot of my project done. I'm sure there is much more. Your strong support makes me confident to explore more details in future." -Rolf Kemper, Manager, Mixed Signal Design, Renesas Electronics Europe "We were very pleased with your response. The VHDL2Verilog translator worked great, even handling the generate statements in the source VHDL. It met our needs exactly. It was very easy to work with you and you delivered the translator super fast. Thanks for the great support!" -Jerry Frenkil, VP of Engineering, NanoWatt Design "EDAUtils is one (if not the only one) of the most comprehensive tools for SoC design and integration and it is available for free. I included EDAUtils in the latest OpenTech Package as featured application among all free open source designs and tools and I believe with a lot of efforts it will grow to be one of the major tools in this domain."- Jamil Khatib, OpenTech Package
Verilog and VHDL Sort Utility ( 0.3.0 Release )