Baya - Auto Integration of SoC Components with IP-XACT & Tcl API
This utility has been developed for those who wants to convert an existing verilog design into SystemC. Such translation is required to mdel an existing IPs after re-architecting the same. This has been developed in Java( 1.6.x ) in order to make it platform independent and bundled as an executable JAR file.
Usage:
source setup_env.('csh' or 'sh' or 'bat' as applicable )
Alternatively, for Unix
setenv EDAUTILS_ROOT /usr/user1/DesignPlayer-linux.x86/01MAY2014 ( installation dir )
set path = ( $EDAUTILS_ROOT/bin $path )
and for Windows
set EDAUTILS_ROOT=D:\tmp\DesignPlayer-win32.x86_64\01MAY2014 ( installation dir )
Use the switch -two_value_logic in case you want to translate the design in the 2 value logic( '0' and '1' ) based SystemC.
You can provide verilog files in any order even as *.v ( inside the lits file ) and use the -sort switch to sort them internally before processing them.
It generates a Makefile in the output directory in order to compile the generated files in the right order and to link them to build the executable.
Get all the options by executing it as 'verilog2systemc -help'
Send your feedback to help@edautils.com for further improvement of this tool.