Available Free EDA Tools( all in Java )
- DesignPlayer- unified GUI platform which encapsulates utilities such as verilog & VHDL testbench generators, verilog module flattening, verilog to vhdl translation and all the utilities listed below. Click here to see demo online and click here to get more details of this tool.
- VHDL RTL Parser(alpha) - parses synthesizable RTL and populates the object models. It contains decompiler API to revert back the RTL or the modified object model. Click here to see demo online and click here to get more details of this tool.
- Verilog RTL Parser- parses synthesizable RTL and populates the database object model. It contains decompiler API to dump out the RTL back or the modified object model. Click here to see demo online and click here to get more details of this tool.
- Verilog Netlist Parser - parses netlist and structural designs and populates its object models. It contains decompiler APIs to dump out the Netlist database and/or the modified database. Click here to see demo online and click here to get more details of this tool.
- sortvhdl and sortverilog (Intuitive VHDL and Verilog Sorting) - it takes just a list of vhdl and verilog files( in any order ) without the VHDL library details. It analyzes the dependencies by computing the VHDL binding information along with default bindings and finally comes up with the sorted list of RTLs. It also dumps out a script which can be used to compile the RTLs with Modelsim. It works even if there is minor syntax or semantic error(s) in the input RTL. Click here to see demo online and click here to get more details of this tool.
- gentbvlog - A Verilog Testbench generator which generates verilog testbench with random stimulus from the given verilog top module. Click here to see demo online and click here to get more details of this tool.
- gentbvhdl - A VHDL Testbench generator which generates VHDL testbench from a given top entity. It does not support user defined datatype in the input/output ports in the top entity. Click here to see demo online and click here to get more details of this tool.
- Clock and Reset tree Anlyzer & tracing- utility to trace clock and reset tree in entire design. Feel free to send your suggestion or send mail if you want to try this utility.
- VHDL2C++ or VHDL2SystemC - Work in progress. Feel free to send your suggestion or send mail if you want to try this utility.
- Configurable RTL/IP generator- Work in progress. Feel free to send your suggestion or send mail if you want to try this utility.
- Intuitive UPF Editor- Work in progress. Feel free to send your suggestion or send mail if you want to try this utility.
- Looking for a different utility ? - Click here to send your requirements
